For the design of an electronic circuit device, such as an integrated circuit chip, typically a team of designers creates the logic structure of the electronic device in terms of a so called netlist which describes which cells of the device have to be interconnected. Typically each cell is identified by a unique logical address.
In the physical implementation of the electronic device the logical address has to be translated to a physical address when the cell is to be accessed. By means of the physical address a pair of signals is selected. In the case of a memory device this can be the word and the bit lines of the memory cell to be accessed.
Generally, a specific cell is selected by selecting the appropriate signal pairs which correspond to a physical address. For each signal there is one physical net implemented in the circuit structure of the device. The cell to be accessed is interconnected to both nets which carry the signal pairs. Thus the area of coincidence of these two nets is representative of the physical coordinates of the cell to be accessed in the layout topology.
As a consequence the logical addresses of an electronic device have to be interrelated to the actual physical placement of the corresponding cells in the layout. Usually this is done either by hand coding a program dedicated to a specific electronic device which can not be used for other devices.
An alternative method is to use a special kind of encoder which requires a comprehensive description of the electronic circuitry including design, layout and a read only memory describer. Each time the physical layout is changed, the encoder has to be changed accordingly which requires a lot of coordination between the layout and design groups of the development staff. This is expensive both in terms of development time and money.
Another instance where a mapping of a logical address to the layout is needed is in circuit testing. When an electronic circuit structure is tested, such as an integrated circuit chip, typically a number of automated test procedures is employed which feed a high number of sequences of test data to the circuit and evaluate the result. Thereby defective logical addresses can be found.
The problem encountered in such a test environment is to determine the physical cell in the circuit structure which corresponds to a defective logical address. This can be important for repair purposes of the circuit or to determine the reason for the failure. Also sometimes it is desirable to examine cells which neighbor the defective cell since it can be likely that they are also affected by the defect. Such an analysis requires a dedicated effort of bit mapping program coding in the prior art.
The underlying problem of the invention is therefore to devise an improved method for mapping of logical addresses to a layout as well as an improved test method and electronic device.